FPGA target = VCU118 9P Xilinx FPGA (Vivado 2020.2) changed to .mem from .coe for versal Energy Et bit width = 10 bits Number of Evnets = File purpose : Eg. ATLAS, GEP MUX --> FPGA RAW data set Header : Yes Line width = file depth (# of lines) = 2 header lines n 2sigma(s) lines ( flag block 0\off 1\on) m Non wrapping, non delimited Energy in order of 2sigma flags

Collapsible text is great for longer section titles and descriptions. It gives people access to all the info they need, while keeping your layout clean. Link your text to anything, or set your text box to expand on click. Write your text here...

Collapsible text is great for longer section titles and descriptions. It gives people access to all the info they need, while keeping your layout clean. Link your text to anything, or set your text box to expand on click. Write your text here...