Time Line
Global Event Processor Firmware
PreproLAr1 v3 Versal FPGA Target
TASK List
Complete On Going and to start
31 Nov 2024
VCU118 PreproLAr1
FW algorithm integration to
develop branch git repository
10 Dec 2024
Previous Versal version
of algorithm updated & tested
with same last vcu118 data test (but Hex),
output matched
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3rd Feb Overleaf Outline Approved by Group
-
overleaf link
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Gdoc links: Outline / DataFlowDoc
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17 Feb draft to group leads, with most content included.
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3rd March Draft to group leads.
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17th March: minimal docs to community.
Large Data Test
Update Block Diagram
31 March 2025, upgrade week
TAP Documents PreproLAr1 FW Algorithm
- describe all steps
- interweave cells list for towers,
needs description
- GEP data handler
- cell processing aspect maybe still in PDR,
MGTs, boards, but
May 2025 : PDR
git Integration / merge request
Versal, PreproLAr1 v3.0.0 Trigger Firmware
Vivado Cluster SLRUM or LSF?
Archives and Documentation updates
- Tier 3
- Lab computers
- Diagrams
- Firmware Test results
- Tasks & Time Lines
- G-docs add/update
- Features/Specs updates
3rd IPBus Data injection test